Many of the discussions on phase-locked loop have been provided in a co-pending application Ser. No. 08/555,941, filed by the same co-inventors, the content thereof is incorporated herein by reference. Basically, a phase-locked loop (PLL) is an electronic circuit for locking an oscillator in phase with an input signal. In other words, a PLL is an electronic circuit for synchronizing, in frequency as well as in phase, an output signal with a reference signal. A PLL can act as a demodulator to demodulate a carrier frequency, or it can be used to track a carrier or synchronizing signal whose frequency varies with respect to time.
PLLs have found a variety of important applications in, for example, communication systems, computers, television engineering, etc. In general, PLLs can be classified, based on its method of implementation, into three main types: analog, mixed digital/analog, and all digital PLLs. A basic analog PLL consists of a phase detector and a low pass filter with a feed back loop closed by a local voltage-controlled oscillator (VCO). The phase detector detects and tracks small differences in phase and frequency between the incoming signal and the VCO signal, and provides output pulses that are proportional to the detected difference. The low-pass filter removes alternating current (ac) components to provide a direct-current (dc) voltage signal to drive the VCO. The input voltage will act to change the output frequency of the VCO to that of the input signal. The phase detector and low-pass filter function as the mixer in a general feedback loop. The output is driven in the direction that will minimize the error signal, such as in frequency. Accordingly, the loop tends to drive the error signal back toward zero frequency. Once the two frequencies are made equal, the output from the VCO will be locked into the input signal, and any phase difference between the two signals will be controlled.
Recently, all-digital PLLs have been developed which provide several advantages over the analog PLLs, including: (1) high yield rate from the IC process; (2) relatively low cost; (3) high stability; (4) can be implemented without external components, such as VCXO, loop filter, etc.; (5) can be implemented with a very narrow loop bandwidth; and (6) can be implemented in a single PLD, thus fostering system development. Some of the most commonly used digital PLLs include SN54LS297 and SN74LS297, both are available from Texas Instrument. The two chips are essentially identical in specification except that the former can operate at a broader temperature range (-55.degree. C. to 125.degree. C.) than the latter (0.degree. C. to 70.degree. C.).
While the all-digital PLLs provide many advantages over their analog counterparts, there is also a very important drawback: they need a substantially higher frequency system clock than the input clock to divide the input clock period into a fractional of the unit interval (UI). The extent to which the system clock must be faster than the input clock depends on the maximum permissible output jitter. For an El-rated output (2.048 M Hz), if the maximum allowable output jitter is to be controlled below 1/32 UI, the conventional all-digital PLL would need a system clock with a frequency as high as 131.072 M Hz or 65.536 M Hz. The requirement of such a high frequency system clock can substantially increase the design complexity and the cost thereof.
In an article entitled: "PHDPLL for SONET Desynchronizer", by Chii-Min Loau and Ji-Tsu Wu, it is disclosed a phase-hopping digital PLL (PHDPLL) for high-speed desynchronization which provided very narrow bandwidth (below 1 Hz). The PHDPLL included the conventional EXclusive-OR (EXOR or XOR) phase detector and a phase-hopping digitally controlled oscillator (PHDCO). The PHDPLL uses the delay time of a basic gate (e.g., a buffer or an OR gate) to cause a phase hopping and thereby a phase step, and does not require a system clock which is required by a conventional all-digital PLL. However, the gate delay utilized in the PHDPLL is highly susceptible to variations due to fluctuations in the local temperature, manufacturing process, operating voltage, etc. The variation in the gate delay can range from as high as twice as much as the designed value to as low as one-half of the designed value. Such a large variation in the intended gate delay can result in failures in attempting to acquire the lock-in, or generate a large output jitter.
In the co-pending application Ser. No. 08/555,941, it was disclosed an improved all-digital PLL which can reduce the required frequency of the system clock by 75%, thus greatly reducing the production cost of PLLs. However, it still needs a relatively high frequency system clock. The PHDPLL does not require a high frequency system clock; however, its performance has been largely unsatisfactory. As discussed before, the variations in the gate delay times can range from as high as twice the designed value to as low as one-half of the designed value. In order to minimize output jitters, the delay time of each delay gate (assuming all the delay gates have the same delay time), .PHI., is designed such that .PHI.L is as close to 2.pi. as possible (but still less than 2.pi., L is the total number of the gate delays). Under this "optimum" design, a small increase in the gate delay (due to change in temperature, process, and/or voltage) can cause the delay time of .PHI.L to be greater than 2.pi., and the loop will become unstable.
Theoretically, the PHDPLL can be "underdesigned" (i.e., by designing the delay gate such that .PHI.L is substantially smaller than 2.pi.) to avoid the above-mentioned instability. However, this would cause large output jitters to be experienced under normal conditions, and is thus highly undesirable. Furthermore, since the gate delay time can be decreased as a result of the changes in environmental variables such as temperature, process, and/or voltage. This factor itself would cause the PHDPLL to be operating away from the optimum condition and result in large output jitters even without an underdesign.
Because of the above mentioned shortcomings, there exist needs to design an improved all-digital PLLs which can be implemented without a high frequency system clock, provide the required stability with minimum output jitter. And most importantly, its stability is independent of temperature, process, voltage and other environmental variations.